Timed decision table and its applications in pre-synthesis and partial synthesis of digital circuits
Rajesh K. Gupta, Jian Li · 1999
We present a new tabular model called Timed Decision Table (TDT) for behavioral and register-transfer level representation and optimization of digital circuits. This model is used to implement assertion-based optimizations and to explore control versus data operation tradeoffs for digital circuit synthesis. We have used this model to implement pre-synthesis optimizations on circuits described in a behavioral Hardware Description Language (HDL). These optimizations are carried out on the HDL source and produce an optimized HDL description that is structured to produce improved synthesis results. One of the pre-synthesis optimization techniques is HDL code restructuring using merging and decomposition transformations on TDTs. These transformations allow us to transform a designer-specified behavioral description, often organized in a subprogram structure that best serves the purposes of conceptualization and programming convenience, into one more suitable for synthesis. This TDT-based approach to HDL analysis and transformations also allows us to identify mutual exclusivity in any operations to better explore the interaction between scheduling and binding tasks in architectural synthesis tools. The TDT model semantics and transformations have been implemented in a tool called PUMPKIN. Using PUMPKIN a designer can analyze, apply assertions, and restructure HDL code. PUMPKIN has been used on a set of high-level synthesis benchmarks leading to improvements of 3%–15% in synthesis results.