SOME FUTURE DIRECTIONS IN FAULT MODELING AND TEST PATTERN GENERATION RESEARCH
F. Joel Ferguson, Tracy Larrabee · 1992
This document presents the current state of fault modeling research and lists research options that leverage the Carafe--Nemesis software packages and the knowledge gained from their use. 1 Current State of Fault Modeling Research The most widely accepted fault model is the single stuck-at (SSA) fault model. It is easy to use and it models many defects that occur in digital circuits, especially TTL circuits [TBG + 83]. If all SSA faults are covered by a test set 1 , each signal line in the circuit has its value observed through sensitized paths at least twice --- once as a logic 0 and once as a logic 1. Due to this nice property, many non-SSA faults are fortuitously detected by SSA test sets. However, as quality level requirements become more stringent the non-SSA faults that remain undetected may cause an unacceptable number of faulty ICs to pass manufacturing test. We now introduce some terminology for which no standards have been set. A defect or spot defect is a local (less t...