Reduced Complexity Input Buffered Switches
Koushik Kar, T. V. Lakshman, Dimitrios Stiliadis, Leandros Tassiulas · 2000
Input-Output buffered crossbars are popular building blocks for scalable high-speed switching because they require minimum speed-up of memory bandwidth. Scaling the design of crossbar switches to large capacities is limited by technology issues such as the reconfiguration of highspeed fabrics or power consumption. In addition, when crossbar architectures are used in the context of IP networks where packets are of variable size, they typically schedule and transfer fixed size envelopes. Incoming packets are fragmented into envelopes and this fragmentation can lead to, possibly large [1], loss of bandwidth and instability. This paper proposes a new method for switching variable sized packets over a crossbar switch that i) allows maximum utilization of switch bandwidth and avoids the fragmentation effect, and ii) allows designers to use much larger envelopes for transfering data over the fabric that minimizes the reconfiguration frequency of the fabric. Reducing the scheduling frequency m...