Input/output performance modeling and interface synthesis in concurrently communicating systems
Janaki Akella · 1992
Inter-process communication within computer systems is becoming increasingly important due to the recent trend of integrating various types of subsystems and system architectures. In the past, heterogeneous computer networks were used, but each computer was itself homogeneous in that all its subsystems followed the same protocol. But the proliferation of specialized applications, such as input/output and networking, has resulted in the necessity to integrate various types of subsystems within the computer system. These subsystems may not have been originally designed to communicate with one another, therefore their integration constitutes a heterogeneous computer system, where even small mismatches in protocols will either result in a performance degradation or in the extreme case prevent interoperation within the system. This thesis attempts to examine the impact of inter-process communication on system performance by direct measurements and to develop a general approach for synthesizing interfaces in concurrently communicating systems by the use of an appropriate process model. Two distinct contributions are made to the area of inter-process communications: modeling and measurement of the impact of input/output on system performance, and automatic synthesis of interfaces to backplane buses. The I/O subsystem's impact on system performance is shown by modeling the relative performance of VAX uniprocessors with and without enhancement in the I/O subsystem. Traditional system performance models were enhanced to include the effect of the I/O subsystem. The parameters modeling the I/O subsystem's effect were identified as $D\sb{I/O}$ (the number of I/O bytes transferred per instruction executed by the CPU), $tr\sb{I/O}$ (the transfer time per I/O byte), and $W\sb{q}$ (the waiting time in the I/O subsystem). These parameters were measured on a VAX11/780 system by using special purpose hardware and were used to calibrate the enhanced system performance model. It is interesting to note that these measurements indicate that contemporary systems require a eight-fold increase over the I/O bandwidth requirement stated by the Amdhal-Case rule. A new approach for automating interface synthesis based on modeling the different subsystem protocols by finite state machines (FSMs) is proposed. The FSM model is more appropriate because of its intimate relationship to regular languages and grammars that makes it possible to automatically generate the FSM corresponding to the interface behavior in the form of transition tables from procedural language interface descriptions. Transition tables of interfaces to four-phase and two-phase handshaking protocol, the VME bus, the MultiBus, and the ATbus have been generated from their high-level language descriptions. These FSMs have also been used to synthesize converters between the different interface protocols by converting the FSM to its corresponding labelled transition system (LTS) and using LTS product reduction techniques.