CORRECTNESS AND REDUCTION IN TIMED CIRCUIT ANALYSIS
Eric G. Mercer, Chris J. Myers, Peter A. Beerel, Ganesh K. Gopalakrishnan, Reid R. Harrison, Priyank Kalla, John Mathews, David S. Chapman · 2003
To increase performance, circuit designers are experimenting with timed circuits -- a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss