Evolutionary Design of Synthetic RTL Benchmark Circuits
Zdeněk Kotásek, Tomáš Pečenka, Josef Strnadel, Lukáš Sekanina · 2004
In the paper it is demonstrated how evolutionary techniques can be used for the process of generating benchmark circuits covering a wide scale of testability properties. To calculate the value of fitness function the approach based on analytical evaluation of testability parameters is used. The solutions which cannot be synthesized by a design system are avoided from the process of developing a new generation of benchmark circuits. The output of the methodology developed and implemented is in the form of component VHDL code. The results are discussed and trends for the future research in this field are indicated. 1