Field Programmable Gate Arrays in 2004
Peter Alfke · CERN Document Server (European Organization for Nuclear Research) · 2004
This paper describes recent progress in Field Programmable Gate Arrays.The title refers to 90-nanometer manufacturing technology, 11 Gigahertz serial I/O, and a sub-femtosecond capture window causing flip-flop outputs to go metastable.There are three main sections: A bird's eye view of FPGA technology, a detailed description ofFPGAs in 2004, and two special problems and solutions I. FPGA TECHNOLOGY A. Lower cost Moore's Law is alive, smaller geometries and larger wafers and lower defect density achieve higher yield, and thus lower cost per function.State-of-the-art is 90 nm on 300 mm wafers Spartan-3 uses this technology for lowest cost One LUT + flip-flop did cost $1.00 in 1990, only $ 0.002 in 2004.Rapid price reductions, driven by intense competition B.More logic and better features: >100,000 LUTs & flip-flops >200 BlockRAMs and 18 x 18 multipliers 1156 pins (balls) with >800 GP I/O 50 I/O standards, incl.LVDs 16 low-skew global clock lines Multiple clock management circuits On-chip processor(s) and Gbps transceivers C. Higher speed Smaller and faster transistors 90 nm technology, using 193 nm u.v.light Cu interconnect ( instead of Al ) was easily achieved.Low-K dielectric progress is slow System speed: up to 500 MHz, mainly through smart interconnects, clock management, dedicated circuits, flexible I/O.Integrated transceivers running at >10 Gbps Speeding up GP logic is getting difficult D. Better tools Back-End Place&Route and XST synthesis.VHDL and Verilog becoming entry point.IP/Cores speed up design and verification.Embedded Software Development Tools support architectures and merge HW and SW.Domain-Specific Languages.System Generator bridges the gap between Matlab/Simulink and FPGA circuit description.ASIC-size FPGAs need ASIC-like tools.ASIC-like size requires ASIC-quality tools.E. ASICs are losing ground ASICS are only for extreme designs: extreme volume, speed, size, low power Cost of a mask set for different technologies: 250 nm: $ 100 k 180 nm : $ 300 k 130 nm: $ 800 k 90 nm: $1200 k 65 nm: $2000 k plus design, verification and risk F. Evolution Every 5 years: System speed doubles, IC geometry shrinks 50%.Every 7-8 years: PC-board min trace width shrinks 50% G.The ever shrinking circuitry Number of LUTs + flip-flops + routing that fit on the cross section of a human hair: • 2000 2 LUTs in Virtex-II (150 nm) • 2002 3 LUTs in Virtex-IIPro (130 nm) • 2004 4 LUTs in Virtex-4 (90 nm) • 2005 8 LUTs = one CLB in 65 nm Moore's law is alive and well in FPGAs