Clustered Instruction-Level Parallel Processors
Paolo Faraboschi, Giuseppe Desoli, Joseph A. Fisher, Uhjlvwhu Edqgzlgwk, Vlqfh D W Slfdo, Rshudwlrq Uhtxluhv, Uhjlvwhu Dffhvvhv, D Lvvxh, Vxshuvfdodu, Pljkw Uhtxluh, Shu F Foh, Phgld Surfhvvru, Pljkw Uhtxluh Dffhvvhv, Fhqwudo Uhjlvwhu, Iloh Ehfrphv · 1998
VLIW, registers, clustering, compilers, EPIC, scheduling CPUs with a large amount of instruction-level parallelism must carry out many register accesses each cycle. Eventually this leads to severe hardware bottlenecks and a loss of cycle time. A solution that has been proposed and implemented a few times is “clustering”. Clustered ILP CPUs have several groups of hardware each consisting of a register bank and one or more functional units. Functional units may only access registers in their associated bank. To access registers in other banks, explicit or implicit intercluster moves must be made while a program is running.