A bit-serial word-parallel finite field multiplier using redundant basis in F 2 M
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi · Communication Systems and Networks · 2007
A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid architecture of the proposed design provides designer the ability to set the trade off between area and delay during the design process.