Realization of the Round 2 AES Candidates using Altera FPGA
Viktor Fischer · 2000
This paper presents an evaluation of five Round 2 Advanced Encryption Standard (AES) candidates from the viewpoint of their realization in a FPGA. After the analysis of the general characteristics of the algorithms a general cipher structure is defined. Using this structure, the suitability of available FPGA families is evaluated. Finally, three algorithms -- RIJNDAEL [5], SERPENT [6] and TWOFISH [7] - are realized in VHDL and implemented in the selected FPGA family. 1. Introduction One of restrictions given by the NIST on the AES candidates was the possibility of their hardware realization. Two conferences have been organized for AES candidates presentation and evaluation. But few assessments of hardware implementation of the proposed algorithms have been published up to now [2]. The final report of the first round [8] has explicitly asked designers for hardware implementation evaluation of all algorithms. The aim of this paper is to evaluate AES candidates from the viewpoint of th...