An Overview of Formal Hardware Specification Languages
A.S. Bunker, Sally A. McKee, Ganesh Lalitha Gopalakrishnan · 2008
Verification is widely recognized as one of the most difficult aspects of computer hardware design. The gap between design and verification capabilities grows, as does the cost of missed flaws. Many researchers investigate ways to formally verify processor designs, interconnects, and protocols, but creating verification methods and tools will remain a central problem for computer scientists for at least the next decade. We introduce this field by surveying formal specification languages. We construct a taxonomy of languages and discuss the applicability of each to standard compliance verification, or demonstrating that a hardware design complies to an interconnect standard.