Soft-Core Processor for Low-Power Embedded Multicore SoCs
Abderazek Ben Abdallah · Atlantis ambient and pervasive intelligence · 2013
Since conventional processors are already capable of starting one operation per cycle, reducing CPI further requires starting more than one operation per cycle. To extract ILP (Instruction Level Parallelism), these processors keep many in-flight instructions, use dynamic scheduling, and register renaming (Smith and Sohi 1995). As results, hardware complexity, power dissipation, and resource underutilization in these architectures become critical performance limiting factors (Tiwari et al. 1998). There are many efforts in architectures design that address these problems. Thus, computer architects are continuously challenged to bring innovations to design micro-architectures, instruction set, and compilers, which help to keep the balance between performance, complexity and power. Several processors have achieved success as two or four-way Super-scalar implementations. However, adding still more functional units is not useful if the rest of the processor is not capable of supplying those functional units with continuous and independent instructions to perform. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.