A 20 MHz CMOS reorder buffer for a superscalar microprocessor
John Lenell, Steven P. Wallace, Nader Bagherzadeh · NASA Technical Reports Server (NASA) · 1992
Superscalar processors can achieve increased performance by issuing instructions out-of-order from the original sequential instruction stream. Implementing an out-of-order instruction issue policy requires a hardware mechanism to prevent incorrectly executed instructions from updating register values. A reorder buffer can be used to allow a superscalar processor to issue instructions out-of-order, and maintain program correctness. This paper describes the design and implementation of a 20Mhz CMOS reorder buffer for superscalar processors. The reorder buffer is designed to accept and retire two instructions per cycle. A full-custom layout in 1.2 micron has been implemented, measuring 1.1058 mm by 1.3542 mm. 1 Introduction A superscalar processor can improve performance by looking ahead into the sequential instruction stream, and executing independent instructions out-oforder. However, issuing instructions out-of-order can cause the processor to execute instructions which sh...