A variable precision processor module
Catherine Yuk-Fun Chow · 1980
This thesis presents one method of designing a variable precision processor module for the four basic floating-point operations. The variable precision module can be used serially by itself or in parallel with identical modules in a flexible manner. Both the precision of the operands and the number of processor modules can be varied without affecting the control of the modules or requiring extra programming effort. The mantissa of the operands are required to be in a signed-digit representation, that is neither maximally redundant nor minimally redundant. The general direction of mantissa processing is from the most significant end to the least significant end. For the majority of the allowed signed-digit representations, a three-level digit slice for which a result digit depends on a maximum of three adjacent digit positions can be defined. A fourth adder level can be added for the rest of the allowed representations. Algorithms for the four basic floating-point operations and three supporting functions are examined for both cases. The size of the digit set is found to affect the cost of the quotient-digit selector as well as the complexity of the algorithms. One organization of the variable precision module is presented to demonstrate the feasibility of the module. The proposed module can be implemented as one VLSI module or with a few building blocks. Furthermore, the complexity of the variable precision module can be adjusted over such factors as the number system and the number of digit slices to fit the implementation limitations. The module requires a small number of inputs and outputs. No extra programming effort is required when two or more modules are used in parallel. This thesis demonstrates the feasibility of the variable precision module and the parallelism implicit in the signed-digit representations.