A modeling technique for specification and simulation of digital systems
H. F. Li, Luc Morin · 1994
In this thesis, a new logic modeling technique based on a mathematical abstraction of analog circuits into logic models is proposed. Many approaches have been used for the modeling of digital systems. They range from pure logic to real time models. Mixed circuit-logic models with switches and strength factors are the most popular in commercial simulators. All of these approaches are meant to provide simple and unambiguous descriptions of the logic devices. However, except in their specification of logic functions and simple timing specifications, they differ in other aspects such as the definition of an event, the number of logic levels, the strength factors, the modeling of wire capacitance and the processing of timing constraints and timing violations. The lack of a consensus is the source of many compatibility problems in modern integrated CAD systems where designers and customers need to share information processed by computers. The objective of this work is to lay down the foundations necessary for such a consensus. The originality of the proposed approach lies in the mathematical formulation of the abstraction mechanism. Precise hypotheses are used to define the logic devices. Then strict construction rules are used to derive their logic models. Three aspects of the logic models are separately considered: the transmission of information over wires using logic events, the propagation delay and the transformation of continuous time to discrete time. A new logic event definition called master-slave events and a new delay model preserving continuity in the modeled logic signal and causality (cause-effect relationship) in the scheduling of the logic events are proposed. Finally, a new graph based algorithm called a Continuous Time Automation (CTA) is described to model logic devices and integrate the input timing constraints with the logic function. A CTA is a finite state machine that processes the sequence of input events and transforms the continuous change of state (continuous time) into a timed state sequence (discrete time). A prototype simulator was developed and CTAs for clocks, pattern generators, gates, combinational circuits, flip-flops, tri-state devices and synchronous sequential circuits are proposed. Without optimization, the performance of the prototype simulator was comparable to many logic simulators for memory requirements, speed and timing accuracy. This modeling technique provides a more accurate logic signal representation, a better model for the physical phenomenon associated with propagation delay and a systematic method to specify and process input timing constraints. It is also easier to use than other logic modeling techniques and it closely matches the engineering approach. On the negative side, the modeling technique is limited to unidirectional signal. However it still permits the use of tri-state busses. Because it accepts and generates analog signals, the proposed model easily interfaces with other circuit models in mixed mode simulation. This work should be useful to someone working on the specification, design, simulation, formal verification and testing of digital systems. For instance, the new modeling technique could be used for the development of primitives in VHDL.