Evolutionary synthesis of multiplexor circuits under hardware constraints
Rolf Drechsler, Wolfgang Günther · 2000
Multiplexor based Field Programmable Gate Arrays (FPGAs) are a very popular design style. However, during circuit design only limited hardware resources are available. In this paper we present an approach to multiplexor (MUX) based circuit evolution under hardware constraints. Binary Decision Diagrams (BDDs) are used as the underlying data structure. An evolutionary technique is proposed that allows to stay within given hardware resources while minimizing the error in parallel. Starting from a correct circuit, i.e. a BDD representing the complete function, some parts are removed, based on evolutionary principles, until all constraints are met. The experimental results presented demonstrate the possibility to handle for the first time instances composed of several thousand gates. 1 Introduction Field Programmable Gate Arrays (FPGAs) have been widely used in implementations of integrated circuits due to several reasons, like short turnaround time and time-to-market as...