The i960CA SuperScalar implementation of the 80960 architecture
Steve McGeady · 2002
The microarchitecture of the Intel i960CA and aspects of the macroarchitecture that allow superscalar implementations are discussed. The i960 architecture has a simple reduced instruction set. It is a three-operand load/store architecture that defines 24 basic instructions, including the normal arithmetic, logical, and memory access instructions, and 16 extended instructions, including a combined compare-and-branch instruction, subroutine call and return instructions, and atomic and synchronous memory access operations. The core of the i960CA processor consists of a single six-ported register file, an instruction sequencer and a set of independent parallel execution units that operate on data in the register file. A careful balance of internal caching, bus bandwidth, and clock speed allows the i960CA to provide a new level of performance without incurring great expense.>