Processor architecture and cache performance
Chad Leland Mitchell · 1986
Previously, analysis of processor architecture has involved the measurement of hardware or interpreters. The use of benchmarks written in high-level languages has added the requirement for the compiler targeted to each architecture studied. Herein, a methodology based on the use of compiler tools has been developed which allows simulation of different processors without the necessity of creating interpreters and compilers for each architecture simulated. The resource commitment per architecture studied is greatly reduced and the study of a spectrum of processor architectures is facilitated. Tools for the use of this methodology were developed from existing compiler and simulation tools. The new tools were validated and the methodology was then applied to study the effects of processor architecture on instruction cache performance. Over 50 architectures from three architectural families (Stack, Register Set and Direct Correspondence) were simulated. Earlier, studies have compared and contrasted the effects of various features of processor architecture. Instruction cache performance has also been studied in some depth. This study provides new results about the relationship between processor architecture and memory traffic for instruction fetches for a general range of cache sizes. Among the results is the general observation that relative instruction traffic differences between architectures are about the same with very large caches as with no cache and that intermediate sized caches tend to accentuate such relative differences.