Building block modeling methodology for composition of microprocessor-based digital systems
Jeffrey Howard Drobman · 1980
The UCLA SARA (System ARrchitect's Apprentice) System is an integrated set of computer-aided tools supporting a structured methodology for design and analysis of hardware and software in digital systems. The structured methodology supported by SARA concludes top-down design (decomposition) with a bottom-up design step (composition) utilizing a library of interconnectable models. This dissertation concentrates on methodology for modeling blocks within the SARA structured, multi-level design environment. While our focus is on microprocessor family type blocks, out intent is to provide methodology applicable to other hardware and softward blocks. The primary hypothesis driving this research has been that a set of computer processable models of hardward and software blocks can be created and utilized as primitive elements in a computer-aided design system (SARA) and methodology such that the composition of requirement-satisfying, partially correct microprocessor-based digital systems is dramatically enhanced. We have contributed to understanding the merits of this statement. We have enhanced intuition of what is a building block (BB) and what is its distinct building (BBM) via examples and formal definition. We have treated the issue of variations of physical BB's by clustering similar versions into one BBM. We have aided the selection of BB's by introducing a taxonomy of BB's. We have aided the creation and usage of BBM's by defining uniformly abstract for the structural (SL1) and behavioral (GMB) sub-models of a hardware BBM; we then demonstrate how these Standard Forms may serve as templates for semi-automatic source code generation for BBM sub-models. We have dealt with validation of BBM's by defining a Test Environment to act as a built-in tester in the model domain. We have introduced the concept of BB's and BBM's to support three distinct functions: (1) gradual immersion into specific detail; (2) necessary modeling of insignificant physical behavior; and (3) modeling artifact required only due to insufficiencies of our present modeling capabilities. The first category involves the modeling of generic classes of BB's established by the taxonomy. The second category includes modeling the behavior of buses which are common in micro-processor-based systems. In SARA, the primary behavioral modeling vehicle is the Graph of Behavior (GMB), which is simulation based. Simulation is limited in that it can only be used to detect errors, but cannot be used alone to prove consistency nor completeness. We have therefore introduced a Socket Attribute Model (SAM) as an attribute-based augmentation to the behavioral modeling capabilities of SARA. SAM provides a static description of the extreme of system dynamics, including the categories of functional intent, electrical characteristics and timing. We have included examples of both complete BBM's (the Am2901 microprocessor and the Am29775 PROM) and design of a 16-bit microprogrammable microcomputer using those BBM's. We have dealt with issues specific to the family of microprogrammable bit-slice elements; horizontal cascadability is a chief property. Moreover, we have defined a Bottom-up Design Procedure (BUD) which utilizes our BBM's. This dissertation research has partially been an investigation into the strength and weaknesses of SARA for modeling off-the-shelf hardware integrated circuits. We intend this research to be extensible to cover chip design using sub-chip BB's, system design using broad-level BB's, and software system design using software BB's.