FPGA-Based Fault-Tolerant Median Denoising Architecture for Impulse Noise Removal in Digital Images
Bhaskar Rao Palakurthi, Rajashekar Kakoju, Jyotsna Devi Jonnalagadda · Zenodo (CERN European Organization for Nuclear Research) · 2026
Impulse noise introduced during image acquisition can severely degrade subsequent vision operations, while hardware acceleration of denoising on SRAM-based field-programmable gate arrays (FPGAs) introduces a second reliability problem: configuration-memory single-event upsets can permanently modify the median-filter logic until the device is reconfigured. This paper presents a compact fault-tolerant median denoising architecture that combines a nine-pixel partial sorting network with a dynamic-range consistency checker. For every 3×3 neighborhood, the median is computed together with the closest lower and upper non-median bounds. A filter malfunction is reported whenever the computed median falls outside this dynamically derived interval, after which partial or complete FPGA reconfiguration can restore the correct configuration. The supplied implementation evaluates the design on 8-bit, 128×128 grayscale images and compares it with dual modular redundancy (DMR) and reduced precision redundancy (RPR). The reported results show that the proposed method requires 385 LUTs, corresponding to 35% logic overhead over the unprotected 286-LUT median filter, compared with 61% for RPR and 100% for DMR. Fault-injection experiments further report detection of 91% of corrupted images. The architecture therefore offers a practical balance between denoising capability, configuration-error awareness, and hardware cost for reliability-sensitive FPGA image-processing systems.