Design of easily testable systems
Sunita Rawat · 1988
Very Large Scale Integration (VLSI) offers a host of opportunities for significant advancement in future electronic systems. One of the main problems heavily affecting turnaround time is fast testing (or lack thereof) of chips. Testability is one of the important attributes of VLSI circuits that has recently received a lot of attention. The testing of Small Scale Integration (SSI) chips was fairly routine. The Large Scale Integration (LSI) chips presented a problem and ad-hoc testing methods were (and are) used to test these chips. As integrated circuit densities have increased the testing problem has become much worse. The cost and time associated with test pattern generation is on the increase. The volume of test data has also become very large. This thesis presents structured testability techniques that can be applied to systolic arrays. Systolic arrays for signal processing have produced processing rates far in excess of general purpose architecture. We consider fast testing as one of the design criteria. Our main goal is to derive test vectors for one- and two-dimensional systolic arrays. We seek to keep the number of test vectors independent of the size of the array under a generic fault model. The testable design is based on pseudo-exhaustive testing. Conventional testing uses Level Sensitive Scan Detection (LSSD) techniques which are very time consuming for an array of systolic processors. By making the testability analysis early the logic designer will be able to make early (and repeated) design trade-offs that make design for testability a simple extension of the design process. The designer must be aware of these issues and the synthesizer, if possible, should present the designer with the best testability versus overhead tradeoff. We show how one-dimensional sequential systolic arrays can be designed so that the faults can be easily detected and isolated. We also consider unilateral two-dimensional sequential arrays and suggest modifications to make them easily testable. Finally we show how a modified carry look ahead adder of arbitrary size can be tested with just 136 test vectors. Comparisons are made against the standard LSSD technique.