Performance issues in VLSI processor design
J. Hennesy, Norman Paul Jouppi, Steven A. Przybylski, Chris Rowen, Tom Gross · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983
MIPS is a new single-chip VLSI microprocessor that achieves high performance with the use of a streamlined instruction set. The software system for MIPS helps obtain a highly effective instruction rate through the pipeline, while the streamlined pipeline structure allows a high clock speed. Performance limitations come from a variety of factors including off-chip communication requirements, internal bus communication delays, and the need for the processor to correctly respond to asynchronous events. 14 references.