Hardware realization of memory-augmented neural networks using multi-level RRAM arrays
Gimun Kim, Yongjin Byun, Sungjoon Kim, Sungjun Kim · Nanoscale · 2026
an incremental step pulse with verification algorithm (ISPVA), validated through hardware-aware Fashion-MNIST simulations. At the array level, 4-bit precision was reliably implemented in a 10 × 24 array, enabling classification of custom digit images with less than 1.8 percentage point accuracy loss compared to software. We further demonstrated in-memory mapping of convolutional kernels (Sobel, Gaussian, and Embossing) through analog VMM. A CNN-based encoder, random-conductance LSH, and differential 0T2R CAM were integrated to form a complete MANN pipeline. Device variability supported similarity-preserving hashing correlated with cosine similarity, while the CAM array distinguished Hamming distances for binary matching. The hardware-aware MANN achieved 83.6% and 90.4% accuracy in 5-way 1-shot and 5-shot tasks, closely matching software performance. These results highlight the promise of in-memory MANNs for low-power, scalable few-shot learning.