A neuromorphic digital Ising solver with Tabu-inspired inhibitory dynamics for scalable graph optimization
Juan Núñez, Rafaella Fiorelli · Neuromorphic Computing and Engineering · 2026
Abstract We present a fully digital Ising solver for maximum-cut implemented on a low-cost Artix-7 field-programmable gate array (FPGA), where tabu-inspired inhibitory dynamics are realized as a compact, Block RAM-resident short-term memory. The solver operates in deterministic fixed-point arithmetic and scales up to the on-chip limit of N = 850 spins across multiple graph sizes and sparsity regimes. We benchmark the proposed Tabu-based dynamics against (i) a parallel Hopfield-network update rule implemented on the same FPGA, and (ii) a CPU-based quantum approximate optimization algorithm (QAOA) reference used as a fixed variational baseline for solution quality under a prescribed budget. Across the tested graph families, the Tabu-enhanced solver reaches higher cut values with reduced run-to-run dispersion than purely deterministic descent. Quantitatively, field-aligned warm start improves the median normalized cut of TS by 0.014 and reduces solve time by 0.18 ms at N = 100 , ρ = 20 % . At the largest tested size ( N = 850 ), TS improves the median normalized cut over the fixed-budget CPU-QAOA reference by 0.014–0.016, with median CPU–FPGA solve-time differences of 640–720 ms under the reported protocol. The N = 850 FPGA implementation closes timing at 100 MHz, demonstrating that short-term inhibitory memory can be embedded in a fully digital Ising network without relying on stochasticity, analog variability, or annealing schedules.