Deterministic Core, Agent Tail: A Verify-Before-Ship Architecture for Orchestrating Open Silicon Sign-Off
Shivaram H Mysore · Zenodo (CERN European Organization for Nuclear Research) · 2026
Language models are being pointed at chip design, but the properties that make them useful (fluent generalization) make them unfit to be an EDA tool: they hallucinate, run non-deterministically, and produce answers that are not auditable. We argue the durable pattern is the opposite of an end-to-end "AI that designs chips": a deterministic core with an agent tail. Put the model on the one irreducibly ambiguous step — interpreting intent or an unstructured input — and make everything downstream deterministic, reproducible, and verified. We instantiate the pattern with Vyges Loom, an open (Apache-2.0) suite of sign-off and optimization engines exposed to a model through the Model Context Protocol over a typed flow intermediate representation, with a verify-before-ship gate that refuses to emit a result the engines cannot confirm. Crucially, the model is never fine-tuned: the engines' typed, self-describing interfaces are the affordance a general model reads and acts on, so expert flows are orchestrated without training the model or hand-coding the flow. Evidence from two independent public tasks — an SoC generation task closed by a single model call plus a deterministic compiler, and an ASAP7 DRC task where the agent shipped a provably valid result rather than an unverifiable guess — shows the core, not the model's scale, carries correctness. The durable consequence: a small, domain-specialized model is sufficient to drive it.