Hardware-Efficient Nonlinear Voltage Threshold Estimation for NAND Flash Memory via Lightweight Deep Learning
Eyal Nitzan, Eviatar Yadai, Assaf Sella, Nimrod Bregman, Avi Steiner, Hanan Weingarten · IEEE Access · 2026
Modern NAND flash memory requires adaptive signal processing to address reliability degradation caused by technology scaling and environmental stress. Conventional NAND flash controllers rely on static, block-level read voltage thresholds (VTs), which fail to capture row-level variations and lead to increased read-retry latency. This work proposes a real-time, nonlinear VT estimation framework for high-throughput NAND flash controllers. The framework enables per-row VT adaptation, while incurring minimal metadata overhead. In particular, VTs are estimated using lightweight deep learning techniques, including deep neural networks (DNNs) with fully-connected hidden layers and entity embeddings. For read-retry scenarios, we introduce a DNN-based VT estimator that leverages optimized sparse sampling of the VT distribution using a small number of additional reads. A hardware-efficient read flow integrating the proposed algorithms is presented. Experimental results on Quad-Level Cell NAND flash memory devices demonstrate significant reductions in added bit error rate compared to fixed and linear VT methods, while maintaining peak performance under start-of-life conditions.