A Comprehensive Survey of Hardware Security in AI Accelerators: A Lifecycle-Aligned Taxonomy of Threats, Defenses, and Emerging Paradigms
Karthi Balasubramanian, Sree Ranjani Rajendran · IEEE Access · 2026
The growth of machine learning (ML) and deep learning (DL) has resulted in the rapid development and implementation of dedicated hardware accelerators, including GPUs, TPUs, FPGAs, and custom ASICs. These accelerators maximize performance and efficiency yet present novel hardware level security vulnerabilities that are not well explored. This survey provides a detailed taxonomy of hardware security threats to ML/DL accelerators, grouping them by attacker, system layer, and stage of the ML lifecycle. We conduct a systematic survey of the current defenses and suggest a unified assessment framework. Moreover, we discuss the security aspects of new paradigms like neuromorphic computing and quantum accelerators. Our survey aims to close the gap between optimization of ML performance and hardware-level security assurance, and point out key research gaps and opportunities to design secure ML hardware. It is the first lifecycle-consistent, cross-layer survey that covers GPUs, FPGAs, TPUs, ASICs, edge, and emerging accelerators, offering an unified reference to researchers and practitioners.