The design of a testable floating point convolution processor /
Jean-François Côté · eScholarship@McGill (McGill) · 1990
This thesis describes the design of a pipeline architecture double precision floating point systolic cell for convolution. The arithmetic operations are distributed into three pipeline stages, enabling the cell to process each set of operands within 16 clock cycles. While offering the same precision obtained on a standard computers, the systolic cell reduces the convolution time expenditure by as much as three orders of magnitude.