Designing power-efficient multi-chiplet processors for data centers : modeling, calibration, and optimization
Sriram Sundaram · 2025
The escalating computational demands of data centers, coupled with the rising cost and complexity of energy delivery, have made power efficiency a first-class design constraint in modern processors. As process technologies scale and architectures diversify through chiplet integration, accurate power modeling and adaptive management have become indispensable for sustaining performance-per-watt gains. This dissertation presents a cohesive framework that unifies pre-silicon power modeling, post silicon calibration, and system-level optimization to address these challenges. First, a Unified Power-Frequency Model (UPFM) is introduced, combining analytical and empirical modeling to enable high-fidelity prediction of power and performance across diverse system-on-chip (SoC) architectures. Second, a self-calibrating silicon framework based on Critical Path Oscillators (CPOs) is developed to measure and adapt to per-die process and environmental variations with sub-FO2 accuracy, closing the loop between modeled and measured silicon behavior. Finally, the dissertation extends these insights to large-scale systems through a hierarchical binning and power allocation methodology for chiplet-based data-center processors, optimizing performance-per-watt across multiple organizational levels — from die to board to rack. Together, these contributions establish an adaptive, closed-loop ecosystem that continuously aligns predictive models with empirical silicon data, ensuring sustained energy efficiency across design generations. The techniques presented not only advance the state of power modeling and calibration but also provide a scalable path to improving efficiency, reliability, and sustainability in the next generation of datacenter computing platforms.