Deterministic Dual-Role I 2 C Verification via Bus Ownership Invariants and Bounded Runtime Switching
Wei Huang, Yu-Cheng Liao, Wei-Chen Lin · IEEE Access · 2026
Dual-role I2C endpoints have become a practical necessity in modern system-on-chip (SoC) architectures, where a single IP must alternate between master and slave roles across boot, recovery, and power-management phases. However, existing verification environments are predominantly designed under static role assumptions, and attempts to retrofit runtime switching often lead to ambiguous bus ownership, unsafe mid-transaction transitions, and concurrency-induced deadlocks. These challenges stem from the absence of explicit safety and progress contracts governing dynamic bus authority. This work presents a deterministic dual-role Universal Verification Methodology(UVM) architecture that formalizes bus driving authority as an explicitly managed resource. The proposed framework defines Bus Ownership Invariants (BOIs) at the open-drain drive-enable interface, enforcing electrical safety directly at the resolution surface. Role transitions are restricted to protocol-aligned commit boundaries—monitor-observed STOP followed by the bus-free interval ($t_{\mathrm {BUF}}$)—ensuring release-before-commit discipline. A bounded event-driven synchronization mechanism further decouples transaction intent from pin-level authority, eliminating cyclic dependencies and guaranteeing deadlock-free progress. Experimental validation using SystemVerilog/UVM and co-simulated I2C RTL models across 165 regression runs demonstrates deterministic mixed-role execution, strict preservation of clock authority in slave mode, and bounded switching latency (median$5.3~\mu s$, maximum$6.2~\mu s$) without long-tail stalls. The resulting methodology provides reproducible safety and liveness guarantees for runtime dual-role verification.