Hardware Trojan Design and Detection in Pre-Charge Half Buffer Asynchronous Circuits
Chukwunalu Asuai, Mousam Hossain, Ashiq A. Sakib, Kushal K. Ponugoti · IEEE Access · 2026
The escalating landscape of cyber warfare has made the detection of hardware Trojans, malicious circuit components capable of leaking sensitive information, a critical research priority. This challenge is further compounded by the rapid integration of artificial intelligence into electronic design automation (EDA) workflows, which has enabled increasingly sophisticated and covert Trojan-insertion techniques. Pre-Charge Half Buffer (PCHB) architectures, a Quasi-Delay Insensitive (QDI) asynchronous paradigm, exhibit intrinsic security advantages and robust tolerance to wide temperature variations. These characteristics position them as compelling candidates for deployment in extreme-environment domains such as space exploration, automotive electronics, the power industry, etc. This paper demonstrates how the dual-rail encoding intrinsic to PCHB circuits can be leveraged to craft stealthy hardware Trojans that circumvent current detection approaches. To systematize these threats, we develop generalized Trojan templates and propose specialized formal verification techniques that enable precise detection at the Register-Transfer-Level. To assess their effectiveness, the detection methods were tested by inserting Trojans into PCHB Rivest-Shamir-Adleman (RSA) decryption cores equipped with key-distribution functionality. Experiments conducted on 28 PCHB RSA benchmarks with varying datapath widths demonstrate that the methodology detects all Trojan behaviors consistent with the defined threat model that become exploitable only when illegal encoding is considered.