Korkean kantaluvun kompleksilukukertojien toteutus FPGA:lle
Aapo Saari · Aaltodoc (Aalto University) · 2018
Multiplication is often the bottleneck in digital signal processing applications. Therefore, faster and more compact hardware multipliers are needed. Multiplication is computed as a series of additions from the hardware point of view. The performance of a hardware multiplier can be enhanced by adding more parallelism at the cost of using more resources. Multiplication of complex numbers is computed as multiplication and addition of real numbers. Therefore, designing an efficient complex number multiplier is a more complicated task than designing a real number multiplier. In this work, we develop multiple complex number multiplication algorithms, along with their respective implementations on FPGA technology. We design the multipliers with the radix-4, radix-8, and radix-16 Booth encoding, as well as the radix-8 non-recoded algorithms. All proposed multipliers are implemented and verified in C++. Catapult HLS tool is used to convert the behavioral models to VHDL, which are synthesizable on Intel Stratix 10 1SX280LN3F43E1VG FPGA. In the next step, we compare the area and performance of the implementations. Finally, we propose the most suitable multiplier for low latency and high performance applications.