Implementation of IP-over-IEEE1394 on FPGA and Its Evaluation
Abu Hassan Mohd Yusairi Bin, KOKI ABE · Institutional Repositories DataBase (IRDB) · 2003
This paper describes an implementation of a subset of TCP/IP protocol suite over IEEE1394interface on FPGA and evaluates the results by counting the logic elements required for the implementation.It is intended for the use in such applications as home networks for transferring andprocessing digital AV data at low costs. By using a system clock of 49.152MHz and 8 terminalsof Data(D0-D7), we observed that packets are transmitted and received between two implementationsvia IEEE1394 port at the transfer rate of 400Mbps. The hardware cost of the IP layer is63% of the link layer’s cost, meaning that the IP-over-IEEE1394 protocol stack can be realizedby hardware by spending an extra cost much less than that of the basic hardware which alreadyexists.