A Novel DFT Architecture and Implementation for 2.5-D Chiplets Based on Test-Bus
Jingrui Hu, Yu Guo, Yan Feng, Xiaolin Tang, Sumin Fan, Guanfei Gong, Zhiqiang Li · IEEE Access · 2026
With the slowdown of Moore's Law, 2.5D/3D Chiplets have become a key solution to break through the bottlenecks of traditional monolithic chips. However, their high integration density poses testing challenges such as pin constraints, cross-layer transmission difficulties, and bonding failure risks, making traditional 2D test architectures incompatible. To address this issue, this paper proposes a test bus-based Design for Testability (DFT) architecture for 2.5D Chiplets. By integrating an interposer-embedded test bus, Bus Network Hosts (BNH), and dedicated Mid-bonding Bypass Modules (MBB), the architecture facilitates comprehensive multi-chiplet testing across both the mid-bonding and post-bonding phases, while natively supporting dynamic assembly scenarios. A 2.5D experimental platform consisting of three chiplets is established for feasibility validation. Synthesis and simulation results demonstrate that this architecture maintains robust timing with minimal area and power overheads, and reduces total test time by 17.5% compared to the multi-component test solution defined by the IEEE 1687 standard. Ultimately, it provides a feasible, efficient, reliable, and cost-effective solution for 2.5D Chiplets testing.