A Scalable Fault-Tolerant and Congestion-Aware Q-Learning Routing Framework for Network-on-Chip Systems
Jitesh Choudhary, Rituraj Das, Chandermani, Ritu Daryani, Imran Hussain Barbhuiya, J. Soumya · IEEE Access · 2026
Efficient and adaptive routing is critical to the performance and reliability of modern Network-on-Chip (NoC) architectures.With the increasing size of NoC meshes, it has become essential that routing algorithms in modern NoCs must be inherently fault-aware and capable of dynamically adapting their routing decisions. This paper presents a Q-learning-based optimal-path routing framework for fault-aware Network-on-Chip (NoC) architectures. The proposed method formulates NoC routing as a Markov Decision Process and introduces a compact, state representation with a reward function designed to be adaptive, enabling a light Q-table which is independent of the size of the mesh, with low memory overhead suitable for hardware deployment. The routing policy is trained offline on a 5 × 5 mesh and evaluated during inference on larger meshes (8×8, 12×12, and 16×16) without retraining. Inference-based results demonstrate comparison of these mesh sizes on the basis of the delivery rate and Hop-Counts required to reach the destination. For hardware-based implementation, a state computation unit has been designed, and the trained Q-table is utilised to test the feasibility of the proposed algorithm on FPGA boards. The simulation results validate that a fault-aware, scalable, optimal, and practically feasible routing algorithm has been proposed.