Secure and Energy-Efficient High-Performance Computing
Mert Side · ThinkTech (Texas Tech University) · 2025
High-performance computing (HPC) is on the verge of the exascale era, yet continued scaling is impeded by three convergent threats: endemic memory-safety constraints in the dominant distributed-memory model and runtime systems, micro-architectural side channels that erode isolation on heterogeneous architectures, and the growing energy footprint of workloads. This dissertation, therefore, poses a unifying question: how can future HPC architectures deliver strong security guarantees and energy-efficient performance without sacrificing scalability? To answer this question, this dissertation advances an integrated, cross-layer design philosophy encompassing architecture, runtime systems, and security capabilities. First, it introduces a secure global memory model by combining the capability model and the Extended Base Global Address Space (xBGAS) model to utilize remote memory access with fine-grained spatial and temporal protection, while incurring minimal latency overheads. This model was validated on the real-world ARM Morello’s Capability Hardware Enhanced RISC Instructions (CHERI) hardware. Second, this dissertation investigates micro-architectural limits and uncovers a novel side-channel that achieves high throughput; it proposes effective countermeasures to suppress this leak. Third, this dissertation designs and develops a workload-aware optimal frequency selection approach for enabling adaptive dynamic-voltage-and-frequency scaling (DVFS). This approach was validated using various common GPU architectures in HPC systems and was demonstrated of reducing energy consumption by up to 30\% at negligible runtime cost. Collectively, these contributions show that our secure global memory model, micro-architectural innovations, and cross-layer power management can be composed into a coherent design for secure, energy-efficient HPC systems. Beyond their immediate practical impact, these findings open new avenues for software-hardware co-design approaches for the secure, energy-efficient exascale systems.