Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack
Lance Fernandes, Stuart E. Wodzro, Prasanna Venkatesan Ravindran, Priyankka Gundlapudi Ravikumar, Minah Lee, Minji Shon, Dyutimoy Chakraborty, Taeyoung Song, Sanghyun Kang, Salma Soliman, Mengkun Tian, Jason Dean Yeager, Jackson Adler, J.M. Chen, Zekai Wang, Douglas Wolfe, Shimeng Yu, Andrea Padovani, Suman Datta, Biswajit Ray · Nano Letters · 2026
High Resolution Image Download MS PowerPoint Slide NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage ( V th ) degradation under ionizing radiation, causing reliability challenges for space and defense applications. Here we show that ferroelectric field-effect transistors (FeFETs) with laminated gate stacks offer a promising route to achieving radiation resilience in vertical NAND technology. We demonstrate that large-memory-window, vertical NAND-compatible laminated poly-silicon-channel FeFETs with an 8 nm Hf 0.5 Zr 0.5 O 2 /3 nm Al 2 O 3 /8 nm Hf 0.5 Zr 0.5 O 2 stack retain a full memory window and robust switching up to 10 Mrad(air) of the total ionizing dose (TID). Programmed and erased states show negligible TID-induced drift after 1 Mrad(air), while only the erased state degrades by ∼2 V at 10 Mrad(air). Technology computer-aided design (TCAD) modeling attributes these asymmetric shifts to state-dependent traps. Compared to charge-trap NAND, laminated FeFETs exhibit ∼30-fold lower V th degradation per unit dose, positioning them as superior radiation-resilient storage candidates.