Bit-sequential VLSI architectures for digital signal processing /
Neeraj Tewari · Lehigh Preserve · 1986
With advances in signal processing and lack of adaptability of general purpose machines, designing special purpose architectures has become increasingly important.Proposed in this thesis are bit-sequential architectures for signal processing algorithms that can be expressed• in either a bilinear form or as a vector-inner product of two time dependent vectors.A three level architecture has been presented for bilinear algorithms and systolic arrays for vector-inner product algorithms.These architectures are modular, employ extensive concurrency and pipelining with localized data and control flow and have a low pin count for input and output, thus making them ideally suited for VLSI implementation.The design philosophy is supported by examples for for FFT butterfly-element, FIR and IIR filters, linear and cyclic convolution and pattern recognition.