Reconfigurable FPU With Precision Auto-Tuning for Next-Generation Transprecision Computing
Guilherme Dias, Luís Crespo, Timo Schlachter, Marc Andre Heller, Jens Krueger, Pedro Tomás, Nuno Roma, Nuno Neves · IEEE Transactions on Circuits and Systems I Regular Papers · 2026
Recent advances in process technology have shifted the research focus from strict raw scaling to the conception of energy-efficient computing units, capable of adapting to the target application precision requirements. A key opportunity lies in floating-point arithmetic, where traditional fixed-precision formats (32/64-bit) often impose unnecessary resources and costs in both performance and power. To address this problem, this manuscript introduces an Automatic Precision Floating-point Unit (APFU) that extends prior reconfigurable designs by incorporating a hardware controller capable of autonomously tuning the operand precision and vectorization levels at runtime. The APFU supports IEEE-754 (double, single, half-precision), bfloat16, and DLFloat formats, and exploits unused datapath capacity to increase the throughput via vector operations. Unlike previous approaches, the proposed APFU introduces a runtime controller that autonomously determines the operand precision and vectorization levels based on operand characteristics and execution mode. The presented experimental evaluation considers an implementation using a 28-nm UMC technology, achieving up to 152 GOPS/W, and demonstrates a detailed analysis across operating frequencies, vectorization modes, and runtime precision adjustment.