Energy-Efficient p-bit-Based Fully-Connected Quantum-Inspired Simulated Annealer With Dual BRAM Architecture
Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu · IEEE Access · 2026
We propose an energy-efficient simulated annealing (SA) hardware design based onp-bits, an emerging class of probabilistic device models. Our approach adopts aspin-serial, replica-parallel architectureand integratesstochastic simulated quantum annealing (SSQA), which emulates quantum annealing behavior using classical hardware. This method accelerates convergence with fewer computational steps while supporting fully connected graphs and maintaining high energy efficiency. To enhance scalability, we introduce adual-BRAM delay-line architecturethat significantly outperforms previous shift-register-based designs. By eliminating the linear fan-out associated with weight propagation in shift-register architectures, our design maintains constant fan-out and on-chip logic usage regardless of the number of spinsN. In contrast to conventional p-bit-based annealing hardware—which stores multiple intermediate spin states and selects the best one—SSQA achieves comparable annealing quality using only the final state, thereby reducing the BRAM footprint for replica states by over 90%. Implemented on a Xilinx ZC706 FPGA, the proposed hardware solves an 800-node benchmark while achieving a 50% energy reduction compared to conventional p-bit-based hardware, which only supports neighbor-connected graphs. It also reduces LUT usage by 97%, FF usage by 88%, and BRAM usage by 70%. These results demonstrate the practicality of p-bit-based annealing hardware for large-scale, fully connected combinatorial optimization problems, offering excellent efficiency in both energy consumption and hardware resource utilization.