Exploring Posit Multiplication: A Comprehensive Review of Booth and Logarithmic Mantissa Methods
Thalla Narasimha Swetha, Uppugunduru Anil Kumar, Syed Ershad Ahmed · IET Computers & Digital Techniques · 2026
The posit number system represents a significant advancement aimed at replacing the current IEEE floating‐point standard in a seamless manner. With its notable dynamic range and gradually tapering precision, a smaller posit can closely match the performance of a larger floating‐point number in representing decimal values. Multiplication is a fundamental arithmetic operation that is essential in a wide range of applications, particularly in fields such as image processing, signal processing, neural networks (NNs), and machine learning. Given the considerable power consumption, area requirements, and latency associated with multiplication, it is imperative to explore optimization strategies in these areas. This article provides a comprehensive review of both exact and inexact (approximate) posit multiplier designs. It includes a detailed comparative evaluation of their error rates and circuit characteristics, aimed at fostering a deeper understanding of the distinctive features of various designs. This study examines Booth‐based posit multipliers and logarithmic posit multipliers, categorizing Booth multipliers into exact and inexact types. The posit multipliers are implemented and synthesized using the Cadence RTL Compiler in Verilog HDL, while error characterization is conducted using the soft posit library in Python. In this article, power, area, and delay are compared in relation to the mean relative error distance (MRED). The comparative results indicate that the logarithmic‐based posit multiplier is hardware‐efficient but has low accuracy. In contrast, the Booth posit multiplier offers superior accuracy, despite having higher performance metrics. Notably, the logarithmic multiplier, referred to as posit logarithmic‐approximate multiplier (PLAM), provides a substantial decrease in power, area, and delay by at least 92%, 82%, and 78%, respectively, compared to all the Booth multipliers. The approximation error of PLAM is analyzed, including metrics such as MRED, to assess performance relative to exact posit multipliers. The posit logarithmic multiplier was validated using various NN architectures, including LeNet‐5, VGG11, and ResNet‐18. The results indicate that posit logarithmic multiplier achieves inference accuracy comparable to traditional floating‐point multipliers while also enhancing hardware efficiency.