VLSI Implementation Of A Systolic Array Viterbi Decoder
Mohd. Noh, Norlaili · Universiti Sains Malaysia Institutional Repository (Universiti Sains Malaysia) · 1995
This project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace-back method can reduce the amount of hardware which is normally a problem with register exchange decoder. It is also suitable for achieving a higher speed of operation as tracking, updating and storage of the information sequence can be accomplished simultaneously during a single clock cycle.