Designing for High Speed-Performance in CPLDs and FPGAs
Željko Žilić, Guy G. F. Lemieux, Kelvin Loveless, Stephen Dean Brown, Zvonko G. Vranesic · 1998
We review some of the techniques for designing with FPGAs and CPLDs used in our design of a large-scale multiprocessor. Several issues concerning high-speed design are addressed: selecting the appropriate programmable logic family, obtaining the fastest circuits with given families, and supplementing the synthesis software. We describe techniques that we used for designing controllers and counters with both CPLDs and FPGAs.