Incremental timing verification in top-down, bottom-up designs using constraint propagation
Sundaravarathan R. Iyengar · 1987
This thesis develops a path analysis approach to incremental timing verification at the logic level. In the bottom up design, timing constraints placed on sub-components are composed and compared against the specified constraints for the entire design. In the top down design, the specified constraints are used to derive partial constraints for the sub-components. If violations are detected, appropriate messages are generated. A graphical editor allows interactive selection and assembly of components from a cell library. A restricted form of temporal logic is used to specify delays and signal relations. A set of rules are used to detect timing violations. These rules may be extended by the user. State equations describe the functional behavior of components. The central contribution in this thesis is the application of constraint propagation techniques to incremental timing verification of digital system designs that supports a hierarchical design methodology. Many contributions made to this area by other researchers have been borrowed and put together in a single framework.