A Network on Chip based gigabit Ethernet router implemented on an FPGA
Andreas Ehliar, Dake Liu · 2006
In this paper we will share the experiences we have gained from implementing an FPGA-based gigabit Ethernet router based on the SoCBUS network on chip architecture. The main reason for this project has been to test the SoCBUS architecture in a real design in order to investigate the performance and possible shortcomings. Another reason is to evaluate how SoCBUS performs in an FPGA. The results highlights several areas where the FPGA implementation of SoCBUS can be improved.