ATLAS: A Scalable Emulator for Transactional Parallel Systems
Christos Kozyrakis, Kunle Olukotun · 2005
With uniprocessor systems running into instruction-level par-allelism (ILP) limits and fundamental VLSI constraints, multi-processor architectures provide a realistic path towards scalable performance. Nevertheless, the key factors limiting the potential of multiprocessor systems are the difficulty of parallel application development and the hardware complexity of large-scale systems. Several groups have recently proposed parallel software and hardware based on the concept of transactions as a novel ap-proach for addressing the problems of multiprocessor systems [1-6]. Transactions have the potential to simplify parallel program-ming by eliminating the need for manual orchestration of parallel tasks using locks and messages [5]. Transactions have the poten-tial to improve parallel hardware by allowing for speculative par-allelism and increasing the granularity of the coherence and con-sistency protocols [4].