POWER and PowerPC
Shlomo Weiss, James E. Smith · Medical Entomology and Zoology · 1994
Foreword Preface 1 Modern Computer Design Concepts 1.1 Introduction 1.2 RISC Architectures 1.3 An Introduction to Pipelining 1.4 Beyond Simple Pipelines 1.5 Instruction Scheduling 1.6 Modern Computer Systems 1.7 POWER and PowerPC: The Big Picture 1.8 The Rest of the Book 1.9 References 2 POWER Architecture 2.1 Introduction 2.2 Instruction Set Basics 2.3 Fixed-Point Unit 2.4 Branch Unit 2.5 Floating-Point Unit 2.6 Virtual Address Generation and Translation 2.7 Protection 2.8 References 3 POWER1 Implementation: Pipelines 3.1 Introduction 3.2 Pipelined Structure of the CPU 3.3 Branch Unit 3.4 Fixed-Point Unit 3.5 Floating-Point Unit 3.6 References 4 POWER1 Implementation 4.1 Introduction 4.2 Solving the Branch Problems 4.3 Branches in the POWER1 4.4 Precise Interrupts 4.5 Interrupts in POWER1 4.6 References 5 POWER1 Implementation: Cache Memories 5.1 Introduction 5.2 Cache Memory Overview 5.3 POWER1 Instruction Cache 5.4 POWER1 Data Cache 5.5 References 6 POWER2: The Next Generation 6.1 Introduction 6.2 POWER Architecture Extensions 6.3 Pipeline Overview 6.4 Branch Unit 6.5 Fixed-Point Unit 6.6 Floating-Point Unit 6.7 Instruction Cache 6.8 Data Cache 6.9 Summary 6.10 References 7 PowerPC Architecture 7.1 Introduction 7.2 Fixed-Point Unit 7.3 Branch Unit 7.4 Floating-Point Unit 7.5 Virtual Address Generation and Translation 7.6 PowerPC versus POWER: Simplification 7.7 PowerPC versus POWER: Extensions 7.8 Summary and Conclusions 7.9 References 8 PowerPC 601 Implementation 8.1 Introduction 8.2 Pipelines 8.3 Branch Processing 8.4 Cache Memory 8.5 PowerPC 601 and POWER1 Implementations 8.6 Summary and Conclusions 8.7 References 9 PowerPC: Support for Multiprocessing 9.1 Introduction 9.2 Architectural Support for Multiprocessing 9.3 Memory Ordering 9.4 Cache Coherence 9.5 Higher-Level Caches 9.6 Cache and Lookaside Buffer Management 9.7 References 10 System Organization 10.1 Introduction 10.2 PowerPC Personal Computers 10.3 PowerPC Multiprocessor Systems 10.4 RS/6000 Workstation Overview 10.5 RS/6000 Main memory 10.6 RS/6000 Input/Output System 10.7 RS/6000 Clustered Multicomputers 10.8 Summary 10.9 References 11 PowerPC 601 and Alpha 21064 11.1 Introduction 11.2 Implementation Overview 11.3 Architecture Comparison 11.4 Summary 11.5 References A IEEE 754 Floating-Point Standard A.1 Floating-Point Numbers A.2 Floating-Point Exceptions B POWER Instruction Format C POWER Instruction Set Sorted by Mnemonic D PowerPC Instruction Formats E PowerPC Instruction Set Sorted by Mnemonic F Cross Reference for Changed POWER Mnemonics Bibliography Index