Silicon architectures for neural nets : proceedings of the IFIP WG 10.5 Workshop on Silicon Architectures for Neural Nets, Saint Paul de Vence, France, 28-30 November, 1990
Mariagiovanna Sami, Jesús Calzadilla-Daguerre · Medical Entomology and Zoology · 1991
Neural Networks: Perspectives from UNISYS (J.A. Pastor et al.). Distributed Large Neural Networks on Silicon (J. Ouali, G. Saucier, J. Trilhe). An Application Oriented Development Environment for Neural Net Models on Multiprocessor EMMA-2 (R. Battiti et al.). Comparing Digital Neural Network Architectures (Y. Kashai, Y. Be'ery). Computing With Very Large Numbers of Elements (J.A. Anderson). Neural Network Emulation on Polymorphic Processor Arrays (M. Maresca et al.). An Artificial Neural Net Based on a Ring Architecture (D. Aspinall, G. Brebner, M. Turega). Neural Network Clock Distribution (D.C. Keezer, V.K. Jain). A CMOS Analog Architecture for Adaptive Neural Networks (D. Caviglia, M. Valle, G.M. Bisio). Floating Gates as Adaptive Weights for Artificial Neural Networks (E. Pasero). A Proposal for Neural Macrocell Array (F. Distante et al.). Radix-r Implementation of Neural Nets (A. Antola, R. Stefanelli, G. Storti-Gajani). Towards a General Purpose Neurocomputing System (P. Treleaven, P.V. Rocha). Wafer Scale Integration for the Implementation of Artificial Neural Networks (E.E. Swartzlander, Jr.). An Intelligent Sensor Integrated VLSI Preprocessor/Emulator Facility for Neural Networks (K.E. Grosspietsch, G. Wagner). Better Activation Functions for Back-propagation Training (I. Bellido, G. Fernandez). The Algorithmic Basis of Neurocomputer Design (U. Ramacher). HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training (K. Asanovic et al.). Dual Computing Structures Containing Analog Cellular Neural Networks and Digital Decision Units (T. Roska). VLSI Design of a Neural Signal Processor (J. Beichter, U. Ramacher, H. Klar). Design and Implementation of a Dedicated Neural Network for Handwritten Digit Recognition (P.-Y. Alla et al.). Potential Performance Advantages of Delay Insensitivity (C.D. Nielsen, J. Staunstrup, S.R. Jones). Mapping of Neural Networks Specific Architectures onto the Non-planar Chip Surfaces (B. Pernunicic, V. Milutinovic, D. Senicic).