Improved modulo (2n + 1) multiplier for IDEA
Yi-Jung Chen, Dyi‐Rong Duh, Yunghsiang Sam Han · 2007
International Data Encryption Algorithm (IDEA) is one of the most popular cryp-tography algorithms in date since the characteristic of IDEA is suitable for hardware im-plementation. This study presents an efficient hardware structure for the modulo (2n + 1) multiplier, which is the most time and space consuming operation in IDEA. The pro-posed modulo multiplier saves more time and area cost than previous designs. With 16-bit input length, the proposed structure is 9.1 % faster than that proposed by Zimmermann in 1999, and reduces the area about 35.22%. The proposed design enables IDEA to be implemented on hardware with high performance and low cost. Simulation results obtained from CPLD system developed by Altera indicate that the new design has 66Mb/sec encryption/decryption rate under 8.25MHz system clock rate with four pipe-line stages for each round.