Stari: a technique for high-bandwidth communication
Mark R. Greenstreet · 1993
This dissertation presents a novel technique for high-bandwidth communication called STARI, Self-Timed At Receiver's Input. STARI is a hybrid of synchronous and self-timed design techniques. STARI is provably correct, well suited for CMOS implementation, and offers a practical, cost effective approach to interprocessor communication in a multiprocessor. To demonstrate STARI, a CMOS chip has been implemented and is described here. STARI is motivated by limitations of purely synchronous or purely self-timed hardware. This dissertation begins with an asymptotic analysis of the performance of self-timed pipelines. It is shown that self-timed pipelines can achieve linear speedup under an assumption of uniform interconnect delays. However, practical designs have non-uniform interconnect because of the hierarchy of packaging. In these designs, the performance is limited by the latency of the slowest interconnect. To exploit the high-bandwidth offered by STARI in a multiprocessor, each processor node must have a memory system that offers high-bandwidth data transfers to the STARI interface and low latency access to the local CPU. Dual-port memories allow both of these goals to be met. Consistency problems that arise when using dual-port memories are identified and two software solutions are presented and analyzed.